Active-HDL is a fully integrated FPGA design and verification environment with a powerful mixed-language simulator and tools for text based and graphical design entry, project management, HDL verification and design documentation. Our solution provides an efficient (FPGA vendor-independent) environment for end-to-end design processing featuring a multi-vendor flow manager that controls simulation, synthesis and implementation for all devices from Actel®, Altera®, Lattice®, Quicklogic®, Xilinx® and other FPGA vendors, while an easy to use co-simulation interface to MATLAB® and Simulink® facilitates designs with DSP.   Active-HDL supports single and mixed HDL design verification for the VHDL, Verilog®, EDIF, SystemC and SystemVerilog languages.

 

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Active-HDL Microsoft Windows XP/Vista Only FPGA Design and Simulation

Graphical design entry including FPGA vendor primitives Mixed language HDL simulation Pre-compiled FPGA vendor libraries Automatic Testbench generation Import legacy designs Code2Graphics and Graphics2Code DSP design and co-simulation with MATLAB®/Simulink® HTML and PDF design documentation Code coverage analysis and Linting Open IP Encryption

 

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